國立屏東商業技術學院教師歷年研究著作／經歷目錄 95.01

研究成果：　
A. 期刊論文

1. 魏大雅、楊雅惠，“大專生對畢業旅行之線上消費行費 ─ 以高屏地區為例”，Bulletin of National Pingtung Institute of Commerce, Vol. 4, pp. 179-199, October 2002.

2. Dahyea D. Wei, “On the Design of Strongly Fault-Secure and Strongly Code-Disjoint Combinational Circuits,” Bulletin of National Pingtung Institute of Commerce, Vol. 5, pp. 173-188, March 1997.

3. K.C. Zeng, Dahyea D. Wei, “Chaos Alone Does Not Mean Security Yet,” Bulletin of National Pingtung Institute of Commerce, Vol. 4, pp. 175-189, March 1996.

4. K.C. Zeng, Dahyea D. Wei, and T.R.N. Rao, “A Cryptoanalytic Assessment on Gunter’s ASG Clock-Controlled by de Bruijn Sequences,” Bulletin of National Pingtung Institute of Commerce, Vol. 4, pp. 161-174, March 1996.

5. Dahyea D. Wei, Gi-Yong Song, Jung H. Kim, and T.R.N. Rao, “Robust Checksum Tests in Algorithm-Based Fault-Tolerant Matrix Multiplication on 2-D Processor Arrays,” Bulletin of National Pingtung Institute of Commerce, Vol.3, pp. 253-277, February 1995.

6. Dahyea D. Wei, Jung, H. Kim, and T.R.N. Rao, “Complete Checking in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays,” Journal of Microelectronic Systems Integration, Vol. 1, Nos. 3/4, pp. 221-234, 1993.(SCI)

7. K.C. Zeng, C.H. Yang, Dahyea D. Wei, and T.R.N. Rao, “Pseudorandom Bit Generators in Stream-Cipher Cryptography,” IEEE Computer, Vol. 24, No.2, pp.8-17, February 1991.(SCI)

8. K.C. Zeng, C.H. Yang, Dahyea D. Wei, and T.R.N. Rao, “Pseudorandom Bit Generators in Stream-Cipher Cryptography,” IEEE Computer, Vol. 24, No.2, pp.8-17, February 1991. (SCI)

B. 研討會論文

1. 魏大雅, 林雅惠, 黃姿婷, 簡麗如, 陳婷芳, 黃靜雯，“冒險世界戶外學校之行銷推廣 ─ 以大專院校學生為例”, 第一屆觀光休閒暨餐旅產業永續經營學術研討會, April 27, 2001, Kaohsiung, Taiwan.

2. 魏大雅, 楊雅惠, 黃琬婷, 周靖芳, 蔣宗煇, 蔡月華, 蔡佳娟, 劉乃綺, “探討大專生對畢業旅行之線上消費行為 ─ 以高屏地區為例”, 第一屆觀光休閒暨餐旅產業永續經營學術研討會, April 27, 2001, Kaohsiung, Taiwan.

3. Dahyea D. Wei, Gi-Yong Song, Jung H. Kim and T.R.N. Rao, “Robust Checksum Tests in Algorithm-Based Fault Tolerance on 2-D processor Arrays,” Proc. of 1994 International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN’94), pp. 97-104, December 14-16, 1994, Kanazawa, Japan.

4. Dahyea D. Wei, Jung H. Kim, and T.R.N. Rao, “Roundoff Error-Free Tests in Algorithm-Based Fault-Tolerant Matrix Operations on 2-D Processor Arrays,” Proc. of 1994 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT-94), pp. 74-82, October 17-19, 1994, Montreal, Canada.

5. Dahyea D. Wei, Jung, H. Kim, and T.R.N. Rao, “Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays,” Proc. of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT-93), pp. 255-262, October 27-29, 1993, Venice, Italy.

6. G.L. Feng, Dahyea D Wei, and T.R.N. Rao, “A Design Method for Optimal Totally Self-Checking and Code-Disjoint PLA of Combinational Circuits,” Presented at the Indian Computing Congress (ICC-91), December 26-29, 1991.

7. K.C. Zeng, Dahyea D. Wei, and T.R.N. Rao, “d-Functions in Vk(F2) and Self-decimation of m-Sequences,” Proc. of 1991 Algebraic Algorithms and Error Correcting Codes (AAECC-9), Oct. 7-11, 1991, New Orleans, Louisiana, USA. Lecture Notes in Computer Science, Springer-Verlag, No. 539, pp.465-476, October 1991, New York.

8. 大專生對畢業旅行之線上消費行為 ─ 以高屏地區為例”，魏大雅、楊雅惠，屏商院學報，2002年十月，pp179-199

9. Dahyea D. Wei, Gi-Yong Song, Jung H. Kim and T.R.N. Rao, “Robust Checksum Tests in Algorithm-Based Fault Tolerance on 2-D processor Arrays,” Proc. of 1994 International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN’94), pp. 97-104, December 14-16, 1994, Kanazawa, Japan.

10. Dahyea D. Wei, Jung H. Kim, and T.R.N. Rao, “Roundoff Error-Free Tests in Algorithm-Based Fault-Tolerant Matrix Operations on 2-D Processor Arrays,” Proc. of 1994 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT-94), pp. 74-82, October 17-19, 1994, Montreal, Canada.

11. Dahyea D. Wei, Jung, H. Kim, and T.R.N. Rao, “Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays,” Proc. of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT-93), pp. 255-262, October 27-29, 1993, Venice, Italy.

12. G.L. Feng, Dahyea D Wei, and T.R.N. Rao, “A Design Method for Optimal Totally Self-Checking and Code-Disjoint PLA of Combinational Circuits,” Presented at the Indian Computing Congress (ICC-91), December 26-29, 1991.

13. K.C. Zeng, Dahyea D. Wei, and T.R.N. Rao, “d-Functions in Vk(F2) and Self-decimation of m-Sequences,” Proc. of 1991 Algebraic Algorithms and Error Correcting Codes (AAECC-9), Oct. 7-11, 1991, New Orleans, Louisiana, USA. Lecture Notes in Computer Science, Springer-Verlag, No. 539, pp.465-476, October 1991, New York.

　

D. 技術報告及其他

1. G.L. Feng, Dahyea D. Wei, T.R.N. Rao, and J.C. Lo, “A Design Method for Strongly Fault-Secure and Strongly Code-Disjoint PLA of Combinational Circuits,” U.S.L. Technical Report, TR91-4-2, 1991.

2. K.C. Zeng, Dahyea D. Wei, and T.R.N. Rao, “A Cryptanalytic Assessment on Gunther’s ASG Clock-controlled by de Bruijn Sequences,” U.S.L. Technical Report, TR 90-4-4, 1990.

3. K.C. Zeng, Dahyea D. Wei, and T.R.N. Rao, “Chaos Alone Does Not Mean Security Yet,” U.S.L. Technical Report, TR

4. 魏大雅,“A Refinement Approach of Algorithm-Based Fault Tolerance in the Operations of LU Decomposition”, NSC 88-2213-E-251-001, 國科會計劃(主持人).

5. 魏大雅,“Integer Rearranged Hamming Checksum Test for Algorithm-Based Fault-Tolerant Matrix Operations”, NSC 86-2213-E-251-001, 國科會計劃(主持人).